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KS5516 -xx on screen display processor on screen display processor the KS5516 is a bicmos lsi with on screen display function, sync separator & expander function. 24 - sdip - 300 functions ? on screen display ? sync separator and sync detector ? general expander features ? character capacity : 240 ( 24 column ? 10 row ) ? construction of character : 12 ? 18 dots ? 128 kinds of character ? display position : 62 horizontal position : 64 vertical position ? character size : 4 ? 4 times of normal ? blinking : character unit ? background coloring : 8 colors ? synchronous ways : automatic selection internal or external synchronization ? general output : 4 bit ( by serial data ) ? built-in sync separator & sync detector ? built-in 4 fsc oscillation circuit ? ntsc / pal / secam mode ? clamp circuit block diagram ordering information device package operating temprature KS5516-xx 24-sdip-300 - 20 ? ~ +70 ? 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 osd rom osd ram data register addr register input control display osc clamp sync detect vsync det 4fsc display control blue back generator shift register control register internal bias ckt sync sep clamp video mixer 12 afc dvdd p3 p2 color out nc syd afcr fsc avdd cvout sccr cvin dgnd sck acb oscin oscout csb sin p1 clampin agnd lpf afcfil option code information code no. remark - 01 - 04 - 08 english, russian chinese arabian
KS5516 -xx on screen display processor pin description pin no. symbol i/o function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 dgnd sck acb oscin oscout csb sin p1 clampin agnd lpf afcfil cvin sccr cvout avdd fsc afcr syd - i i i o i i p i - - - i i o - i i o digital ground serial clock input. when csb pin is ? then serial data is inputted by micom. hysterisis input. auto clear pin. if ? then all circuits are reset. built-in pull up resistor. hysterisis input. lc oscillation pin. standard frequency is 7mhz & the horizontal start position is controlled by the clock of oscillation block. while pin 6 is low, serial data input is active. built - in pull up resistor serial data input pin. built-in pull up resistor general output port 1 clamp input pin of composite video signal analog ground low pass filter afc filter output composite video signal input secam chroma input composite video output : 2 vp-p analog vdd fsc input vco oscillation frequency control when sync signal is inputted, then syd is high.
KS5516 -xx on screen display processor pin no. symbol i/o function 20 21 22 23 24 nc color out p2 p3 dvdd - o o o - pin description ( continued ) no connection blueback color signal output general output port 2 general output port 3 digital v dd absolute maximum ratings ( ta = 25 ? ) characteristics symbol value unit supply voltage input voltage power dissipation operating temperature storage temperature v dd v in p d topr tstg - 0.3 ~ 6.0 v ss - 0.3 ? v in ? v dd + 0.3 300 - 20 ~ + 70 - 40 ~ + 125 v v mw ? ?
KS5516 -xx on screen display processor electrical characteristics ( ta = 25 ? , av dd = dv dd = 5v ) characteristics symbol unit operating voltage operating voltage operating current pin 12 dc voltage pin 13 dc voltage afc freerun frequency afc pulse width afc delay time afc lock range h afc lock rnage l afc capture range h afc capture rrange l sync det. lock range h sync det. lock range l sync det. capture range h sync det. capture range l v-sync delay time dv dd av dd icc vpi2 vpi3 ffr twd td falh fall fach fac1 flh fll fch fc1 tvd min typ max 4.5 4.5 10 2.25 1.3 15.5 3.7 1.0 +600 - +400 - 143 6.7 100 14.3 10 5.0 5.0 18 2.5 1.45 15.7 4.0 2.5 - - - - 153 7.7 107 15.3 14 5.5 5.5 25 2.75 1.6 15.9 4.3 4.0 - -900 - -700 163 8.7 114 16.3 - v v ma v v khz usec usec hz hz hz hz khz khz khz khz oscillation level oscillation frequency blueback sync tip level blueback pedestal level blueback color burst level h blueback color level h fsc input level vosc fosc vbst vbpd vbbh vbch v fsc 3.0 6.3 1.1 1.75 2.0 2.55 1.2 3.5 7.0 1.3 1.95 2.2 2.75 1.5 4.0 7.7 1.5 2.15 2.4 2.95 2.0 usec vpp mhz v v v v vpp
KS5516 -xx on screen display processor operation description memory structure after recording the serial data from a -com to ram and control register, it is need by h-sync and v sync that detecting from composite video signal, and then mix the character data of rom to composite video signal. when composite video siganl is input, KS5516 outputs the blueback signal by divide and mixture the 4 fsc signal. the following table is data structure from micom. ? memory address consists of 16 bit ? the data of address 0 - 239 is character data which is display on the screen. ? the address 240 - 244 is the control register ? the upper 4 bit don w care bit bit addr 0 239 240 241 242 243 244 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 0 0 0 0 p ch2 ch1 ch0 bli c6 c5 c4 c3 c2 c1 c0 0 0 0 0 p ch2 ch1 ch0 bli 0000pint/ non hsz 21 hsz 20 hsz 11 hsz 10 hp5 hp4 hp3 hp2 hp1 hp0 0 0 0 0 p bli2 vsz 21 vsz 20 vsz 11 vsz 10 vp5 vp4 vp3 vp2 vp1 vp0 0000p 0000p 0000p dsp 3 dsp 2 dsp 1 ram ers test tc lev 1 lev 0 ph2 ph1 ph0 -le bk le cha dsp on blk 1 blk 0 bli 1 bli 0 ex ym bco secam nt/ pal - pd3 pd2 - pd0 pc3 pc2 pc1 pc0 c6 c5 c4 c3 c2 c1 c0 (rom address)
KS5516 -xx on screen display processor control register 1) register 240 da0 ~ daa register state content function 0 1 2 3 4 5 6 7 8 9 a hp0 hp1 hp2 hp3 hp4 hp5 hsz10 hsz11 hsz20 hsz21 int/ non 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 hs is horizontal display start position tc : osc. period ( 1/7mhz = 143 nsec ) hsz11 hsz21 hsz10 hsz20 n 0 0 1 1 0 1 0 1 9 10 11 12 1 v t line 0 1 01 1x 2x 3x 4x 2nd ~ 10 th line 0 1 01 1x 2x 3x 4x interlace mode non-interlace mode remark horizontal start position 1 v t line character size control to horizontal- direction 2nd ~ 10th line character size con- trol to horizontal- direction hs = tc * ^ 4 * ( hpn * 2 ) + n ` n=o 5 n hsz10 hsz11 hsz20 hsz21
KS5516 -xx on screen display processor 2) register 241 register state content function 0 1 2 3 4 5 6 7 8 9 a vp0 vp1 vp2 vp3 vp4 vp5 vsz10 vsz11 vsz20 vsz21 bli2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 vs is vertical start position h : horizontal synchronous pulse time 0 1 01 1x 2x 3x 4x remark vertical start position 1 v t line character size control to vertical direction 2nd ~ 10th line character size con- trol to vertical direction vsz10 vsz11 0 1 01 1x 2x 3x 4x vsz20 vsz21 v - sync 64 divide ( = 1 sec ) v - sync 32 divide ( = 0.5 sec ) hs vs v-sync h-sync vs = h * ^ 4 * ( vpn * 2 ) + 3 ` n=o 5 n control the blink period da0 ~ daa
KS5516 -xx on screen display processor register state content function 0 1 2 3 4 5 6 7 8 9 a ph0 ph1 ph2 level0 level1 tc test ram ers dsp1 dsp2 dsp3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 remark 3) register 242 p2 p1 p0 ntsc pal black e /2 7 e /4 0 e 3 e /4 3 e /2 white black e /2 + e /4 0 2 e 3 e /4 3 e /2 white 01 level 0 level 1 0 1 internal bias 1 internal bias 2 internal bias 3 1h = 454tc 1h = 455tc tc = 2fosc active mode test mode ram no erase ram erase display method of the 1 v t is fixed by blk0 & blk1 display method of the 1 v t is vriable display method of 2nd - 9th is fixed by blk0 & blk1 display method of 2nd - 9th is variable display method of 10 th is fixed by blk0 & blk1 display method of 10 th is variable back ground color control bit color level control - 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 da0 ~ daa
KS5516 -xx on screen display processor register state content function 0 1 2 3 4 5 6 7 8 9 a bco ym ex bli0 bli1 blk0 blk1 dsp on lecha lebk - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 remark 01 0 1 4) register 243 bli1 bli0 off duty 50% duty 25% duty 75% blinking mode control 01 0 1 bli1 bli0 off o c r blinking mode control display off display on character luminance level 1 character luminance level 2 blank luminance level 1 blank luminance level 2 blanking area coloring full tv screen coloring the same character and back ground variable back available external mode available internal mode available determined by blk0 & blk1 determined bybco, blk0 & blk1 blinking duty control c : character o : outline r : raster - - da0 ~ daa
KS5516 -xx on screen display processor register state content function 0 1 2 3 4 5 6 7 8 9 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 remark 5) register 244 0 1 01 pc0 pc1 port output ch1 output 0 1 01 pc2 pc3 hsync/vsync output port output ch2, bli2 output test mode l output h output - - l output h output l output h output - - ntsc mode pal mode ntsc or pal mode secam mode pin 8 output mode setting pin 22/23 output mode setting pin 8 output data setting pin 22 output data setting pin 23 output data setting hsync/vsync output - pc0 pc1 pc2 pc3 pd0 - pd2 pd3 - nt/ pal secam da0 ~ daa
KS5516 -xx on screen display processor test circuit 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 osd rom osd ram data register dddr register input control 4 fsc display control control register blue back generator shift register clamp sync sep vsync det vsync detect clamp afc internal bias ckt display control video mixer + a sw2 b 1uf dv dd color out nc syd afcr fsc av dd cv out 1uf + 100k cv in d gnd sck acb osc in osc out 56p 68p a sw1 b 10uf csb sin p1 clampin a gnd lpf afcfl 4.7uf + 200k 100p 104 1k 0.47uf + p2 p3
KS5516 -xx on screen display processor application circuit the circuit drawn above is for demo board. ? fsc x-tal a ntsc : 3.579545mhz(y102) pal : 4.433619mhz (y101) ? c159 / c160 : the load capacitor of x-tal y101/y102 has a difference each according to its manufacturer. dgnd agnd 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 osd rom osd ram data register addr register input control 4 fsc display control control register blue back generator shift register clamp sync sep vsync det vsync detect clamp afc internal bias ckt display control video mixer syd dgnd sck acb oscin oscout c141 82p c142 68p l106 10uh csb sin p1 clampin agnd lpf afcfil c137 4.7 r173 200k c148 100p c149 122 r147 1k c150 0.33 p2 afcr c143 104 fsc + c144 100 r177 75 1 + r172 100k cv in sccr + c147 1uf + video out + c153 220 q115 a733 + c152 203 c138 dc 2.5v vin : 2vpp vsync: > 0.3vpp 5v q116 9v r176 430 l104 100uh l105 100uh r100 510 c146 100uf c145 104 c151 100uf ka7805 l107 100uh + c157 100uf c158 104 r178 91k q117 c945 c161 68 ? + c163 1 y102 3.579545 ? c159 c160 y101 4.433619 ? r179 91k r180 15k c162 68 ? to pin 17 ntsc pal dvdd p3 color out nc syd avdd cvout

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